FIG. 1 is a circuit diagram showing the first prior art of a high frequency switch circuit. The first prior art will be explained with reference to FIG. 1.
The first prior art concerns an SPDT circuit (Single Pole Double Transfer) disclosed in Japanese Unexamined Patent Publication No. 8-139014. The drains and sources of field effect transistors 1 to 5 are cascade-connected between high frequency terminals 101 and 102. The drains and sources of field effect transistors 6 to 10 are cascade-connected between the high frequency terminal 101 and a high frequency terminal 103. The gate electrodes of the field effect transistors 1 to 10 are connected to resistance elements 51 to 60. The resistance elements 51 to 55 connected to the gate electrodes of the field effect transistors 1 to 5 are connected to a switching signal terminal 111. The resistance elements 56 to 60 connected to the gate electrodes of the field effect transistors 6 to 10 are connected to a switching signal terminal 112.
Voltages at opposite levels are input to the switching signal terminals 111 and 112. When high level is input to the switching signal terminal 111 and low level is input to the switching signal terminal 112, the field effect transistors 1 to 5 are turned on, the field effect transistors 6 to 10 are turned off, and the high frequency terminals 101 and 102 are rendered conductive. When low level is input to the switching signal terminal 111 and high level is input to the switching signal terminal 112, the field effect transistors 1 to 5 are turned off, the field effect transistors 6 to 10 are turned on, and the high frequency terminals 101 and 103 are rendered conductive.
FIG. 2 is a circuit diagram showing the second prior art of a high frequency switch circuit. The second prior art will be explained with reference to FIG. 2.
The second prior art concerns an SPDT circuit disclosed in Japanese Unexamined Patent Publication No. 8-213893. High frequency terminals 101 and 102 are connected by a field effect transistor 1, and the high frequency terminal 101 and a high frequency terminal 103 are connected by a field effect transistor 2. The high frequency terminal 102 is grounded via the drain-source path of a field effect transistor 3 and a capacitive element 71. The high frequency terminal 103 is grounded via the drain-source path of a field effect transistor 4 and a capacitive element 72. The gate electrodes of the field effect transistors 1 to 4 are connected to resistance elements 51 to 54, respectively. The resistance element 51 connected to the gate electrode of the field effect transistor 1 and the resistance element 54 connected to the gate electrode of the field effect transistor 4 are connected to a switching signal terminal 111. The resistance element 52 connected to the gate electrode of the field effect transistor 2 and the resistance element 53 connected to the gate electrode of the field effect transistor 3 are connected to a switching signal terminal 112. The high frequency terminals 101 to 103 and the source electrodes of the field effect transistors 3 and 4 are connected to an external power supply 300 via resistance elements 55 to 59.
Voltages at opposite levels are input to the switching signal terminals 111 and 112. The high frequency terminals 101 to 103 and the source electrodes of the field effect transistors 3 and 4 receive the potential of the external power supply 300 via the resistance elements 55 to 59. When high level is input to the switching signal terminal 111 and low level is input to the switching signal terminal 112, the field effect transistors 1 and 4 are turned on, the field effect transistors 2 and 3 are turned off, and the high frequency terminals 101 and 102 are rendered conductive. When low level is input to the switching signal terminal 111 and high level is input to the switching signal terminal 112, the field effect transistors 1 and 4 are turned off, the field effect transistors 2 and 3 are turned on, and the high frequency terminals 101 and 103 are rendered conductive.
The SPDT circuit is incorporated in, e.g., a portable cellular phone set, and functions as a high frequency transmission/reception signal switch. The field effect transistor used in the high frequency switch circuit is, e.g., a depletion n-channel GaAs MESFET, and is turned on at 0 [V] and off at −3 [V].
The conventional high frequency switch circuit suffers the following problems.
In the first prior art, no potential is externally applied to a high frequency terminal, and high frequency terminals at the two terminals (drain and source sides) of an ON field effect transistor are set to almost the same potential as high level. The potential difference between the gate and the source becomes almost 0 [V], and the ON resistance cannot be sufficiently reduced. That is, the transmission loss increases.
In the second prior art, a potential is externally applied to a high frequency terminal, and a gate-source potential Vgs can be positively increased depending on an application potential VC. The ON resistance can be reduced, and as a result, the transmission loss can be reduced. A maximum handling power Pmax which can be handled by a circuit constituted by cascade-connecting n field effect transistors is given by
 Pmax=2{n(VC−VL+VT)}2/Zo
(where VL is low level, VT is the threshold voltage of the field effect transistor, and Zo is the evaluation system impedance in the switch circuit.)
The difference between low level (VL) and VC becomes small, decreasing handling power. To increase handling power, the number of cascade-connected field effect transistors must be increased. An external power supply is undesirably required.
In other words, in the conventional high frequency switch circuit, signal transmission paths are DC-connected. If Vgs of an ON switch is positively increased to reduce the ON resistance, handling power decreases in an OFF switch. If Vgs of an OFF switch is negatively increased to increase handling power, the ON resistance of an ON switch increases.